MOS circuits, particularly CMOS circuits, are utilized in a variety of applications. For example, these circuits are utilized in level shifters, oscillators, phase rotators, inverters, and the like. It is known that running these circuits at low supply voltages affect the performance of the circuits over process, temperatures and supply voltage variations.
The power dissipation of CMOS circuits is roughly proportional to the square of the supply voltage, and so running these circuits at low supply voltages is important to achieve low power dissipation. However, the performance of many CMOS circuits degrades rapidly as the supply voltage approaches the sum of the threshold voltages of the NMOS and PMOS devices. The threshold voltage of the MOS devices is also a strong function of temperature. Organizing circuit performance for the low-voltage, low-temperature (high-Vt) corner typically results in excessive power dissipation at the high voltage, high-temperature (low-Vt) corner.
There are many techniques that compensate for process, temperature and supply voltage variations. Some of these techniques are diverted to providing a bias voltage to the MOS device(s) to compensate for the above mentioned variations. However, known techniques typically include a feedback loop to control the bias voltage. Other techniques directly compensate for these variations. These known conventional techniques, however, are oftentimes not effective, particularly in low voltage applications.
Accordingly, what is needed is a system and method for compensating for process, voltage and temperature variations in a MOS device(s). The system and method should be cost effective, easily implemented and adaptable to existing circuits. The present invention addresses such a need.